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A Case Study of Hardware/Software Partitioning of Traffic Simulation on the Cray XD1

机译:Cray XD1上交通仿真的硬件/软件分区的案例研究

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Scientific application kernels mapped to reconfigurable hardware have been reported to have 10$times$ to 100$times$ speedup over equivalent software. These promising results suggest that reconfigurable logic might offer significant speedup on applications in science and engineering. To accurately assess the benefit of hardware acceleration on scientific applications, however, it is necessary to consider the entire application including software components as well as the accelerated kernels. Aspects to be considered include alternative methods of hardware/software partitioning, communications costs, and opportunities for concurrent computation between software and hardware. Analysis of these factors is beyond the scope of current automatic parallelizing compilers. In this paper, a case study is presented in which a simulation of metropolitan road traffic networks is mapped onto a reconfigurable supercomputer, the Cray XD1. Five different methods are presented for mapping the application onto the combined hardware/software system. An approach for approximating the performance of each method is derived through analytic equations. Our results, both analytically and empirically, show that key predictors of performance (which are often not considered in reported speedup of kernel operations) are not necessarily maximum parallelism, but must account for the fraction of the problem that runs on the reconfigurable logic and the amount data flow between software and hardware.
机译:据报道,映射到可重新配置硬件的科学应用内核比同类软件具有10倍至100倍的加速。这些有希望的结果表明,可重新配置的逻辑可能会大大加快科学和工程应用的速度。但是,为了准确评估硬件加速对科学应用程序的好处,有必要考虑整个应用程序,包括软件组件和加速内核。要考虑的方面包括硬件/软件分区的替代方法,通信成本以及在软件和硬件之间进行并行计算的机会。这些因素的分析超出了当前自动并行化编译器的范围。本文提出了一个案例研究,其中将城市道路交通网络的模拟映射到可重新配置的超级计算机Cray XD1上。提出了五种不同的方法将应用程序映射到组合的硬件/软件系统上。通过解析方程,得出一种近似每种方法性能的方法。我们的分析结果和经验结果均表明,性能的关键预测指标(在报告的内核操作加速中通常不予考虑)不一定是最大并行度,而是必须解决可重配置逻辑和软件和硬件之间的大量数据流。

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