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A Framework for Power-Gating Functional Units in Embedded Microprocessors

机译:嵌入式微处理器中的门控功能单元的框架

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Power gating is a technique commonly used for leakage reduction in integrated circuits. In microprocessors, power gating is implemented by using sleep transistors to selectively deactivate circuit modules that remain idle for sustained periods of time during program execution. In this work, we develop a new framework for power gating the functional units in embedded system microprocessors without degradation in performance. The proposed framework includes an efficient algorithm for idle time estimation, appropriate insertion of sleep instructions within the code, and a method for reactivating the sleeping units only when needed without the use of wakeup instructions. We introduce the notion of loop hierarchy trees (LHTs) to represent the partial ordering of the nested loops within the program. From the control flow graph (CFG) representation of the source program, a forest of LHTs is constructed and is used to identify the maximal subgraphs representing the long idle periods for the functional units. For each subgraph thus identified, a sleep instruction is introduced in the program with a list of corresponding functional units to be deactivated. When an instruction is decoded, the functional units needed for that instruction are automatically activated by the control unit such that the units are ready before the instruction reaches the execute stage. This eliminates the need for wakeup instructions to be inserted into the object code reducing the overheads. In our implementation, the ARM processor architecture was modified and resynthesized to include power gating by developing a CMOS cell library of functional units with the above capabilities. Experimental results are reported for a set of 12 benchmarks chosen from the MiBench suite, which indicate that, on average, our technique reduces the leakage energy in functional units by 31.1% for integer benchmarks and 26.8% -nfor floating-point benchmarks.
机译:功率门控是减少集成电路泄漏的常用技术。在微处理器中,电源门控是通过使用睡眠晶体管来有选择地停用在程序执行期间保持空闲时间的电路模块而实现的。在这项工作中,我们开发了一种新的框架,用于对嵌入式系统微处理器中的功能单元进行电源门控,而不会降低性能。所提出的框架包括用于空闲时间估计的有效算法,在代码内适当地插入睡眠指令以及仅在需要时不使用唤醒指令才重新激活睡眠单元的方法。我们引入了循环层次树(LHT)的概念来表示程序中嵌套循环的部分排序。根据源程序的控制流图(CFG)表示,构建了LHT的林并将其用于标识代表功能单元长空闲周期的最大子图。对于由此标识的每个子图,在程序中引入睡眠指令,并带有要停用的相应功能单元的列表。当对一条指令进行解码时,该指令所需的功能单元会由控制单元自动激活,以使这些单元在指令到达执行阶段之前就已准备就绪。这消除了将唤醒指令插入目标代码中的需要,从而减少了开销。在我们的实现中,通过开发具有上述功能的功能单元的CMOS单元库,对ARM处理器体系结构进行了修改和重新合成以包括电源门控。报告了从MiBench套件中选择的一组12个基准的实验结果,这些结果表明,平均而言,我们的技术将整数基准的功能单元的泄漏能量降低31.1%,将浮点基准的泄漏能量降低26.8%。

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