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Voltage Scalable High-Speed Robust Hybrid Arithmetic Units Using Adaptive Clocking

机译:使用自适应时钟的电压可扩展高速鲁棒混合算术单元

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In this paper, we explore various arithmetic units for possible use in high-speed, high-yield ALUs operated at scaled supply voltage with adaptive clock stretching. We demonstrate that careful logic optimization of the existing arithmetic units (to create hybrid units) indeed make them further amenable to supply voltage scaling. Such hybrid units result from mixing right amount of fast arithmetic into the slower ones. Simulations on different hybrid adder and multipliers in BPTM 70 nm technology show 18%–50% improvements in power compared to standard adders with only 2%–8% increase in die-area at iso-yield. These optimized datapath units can be used to construct voltage scalable robust ALUs that can operate at high clock frequency with minimal performance degradation due to occasional clock stretching.
机译:在本文中,我们探索了各种算术单元,这些算术单元可以在具有自适应时钟扩展功能的按比例缩放的电源电压下运行的高速,高收益ALU中使用。我们证明,对现有算术单元进行精心的逻辑优化(以创建混合单元)确实使它们进一步适合于电源电压缩放。这样的混合单元是由于将适量的快速算术混合到较慢的算术中而产生的。在BPTM 70 nm技术中对不同的混合加法器和乘法器进行的仿真显示,与标准加法器相比,功率提高了18%–50%,而等产量时,芯片面积仅增加了2%–8%。这些优化的数据路径单元可用于构建电压可扩展的健壮ALU,这些ALU可以在高时钟频率下运行,并且由于偶尔的时钟延展而导致的性能下降降至最低。

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