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首页> 外文期刊>Very Large Scale Integration (VLSI) Systems, IEEE Transactions on >FA-STAC: An Algorithmic Framework for Fast and Accurate Coupling Aware Static Timing Analysis
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FA-STAC: An Algorithmic Framework for Fast and Accurate Coupling Aware Static Timing Analysis

机译:FA-STAC:用于快速准确耦合的静态时序分析的算法框架

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This paper presents an algorithmic framework for fast and accurate static timing analysis considering coupling. With technology scaling to smaller dimensions, the impact of coupling induced delay variations can no longer be ignored. Timing analysis considering coupling is iterative, and can have considerably larger run-times than a single pass approach. We propose two different classes of coupling delay models: heuristic-based coupling model and current source-based coupling model, and present techniques to increase the convergence rate of timing analysis when such coupling models are employed. Our proposed coupling model show promising accuracy improvements compared to SPICE. Experimental results on ISCAS85 benchmarks validates the effectiveness of our efficient iteration scheme. Our iteration algorithm obtained speedups of up to 62.1% using a heuristic coupling model while 2.7$times$ using a current-based coupling model in comparison to traditional approaches.
机译:本文提出了一种考虑耦合的快速准确的静态时序分析算法框架。随着技术规模的缩小,耦合引起的延迟变化的影响将不再被忽略。考虑耦合的时序分析是迭代的,并且与单遍方法相比,运行时间可能要大得多。我们提出了两类不同的耦合延迟模型:基于启发式的耦合模型和基于电流源的耦合模型,并提出了在采用此类耦合模型时提高时序分析收敛速度的技术。与SPICE相比,我们提出的耦合模型显示出有希望的精度改进。 ISCAS85基准测试结果验证了我们高效迭代方案的有效性。与传统方法相比,我们的迭代算法使用启发式耦合模型获得了高达62.1%的加速,而使用基于电流的耦合模型获得了2.7倍的加速。

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