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A Robust Edge Encoding Technique for Energy-Efficient Multi-Cycle Interconnect

机译:节能多周期互连的稳健边缘编码技术

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In this paper, we propose a new circuit technique for on-chip communication, the edge encoding technique, to reduce the energy consumption in multi-cycle interconnects. Both average and worst-case energy are reduced by desynchronizing the edges of rising and falling transitions. In a 1.2 V 65-nm CMOS technology, the proposed approach achieves up to 34% energy reduction with no latency overhead over optimally designed conventional busses due to coupling capacitance reductions. The technique further reduces energy consumption by 39% with iso-throughput at the expense of one-cycle latency. Energy savings are shown to be both larger and more robust to process, voltage, and temperature variations than previous techniques.
机译:在本文中,我们提出了一种用于片上通信的新电路技术,即边缘编码技术,以减少多周期互连中的能耗。通过使上升和下降转换的边沿不同步,可以减少平均能量和最坏情况的能量。在1.2 V 65 nm CMOS技术中,由于耦合电容的减少,与经过优化设计的传统总线相比,所提出的方法可实现高达34%的能量减少,并且没有延迟开销。该技术以等周吞吐量进一步降低了39%的能耗,但消耗了一个周期的延迟。与以前的技术相比,节能效果更大,并且对过程,电压和温度变化的抵抗力更强。

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