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The Effect of Multi-Bit Correlation on the Design of Field-Programmable Gate Array Routing Resources

机译:多位相关对现场可编程门阵列路由资源设计的影响

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As the logic capacity of field-programmable gate arrays (FPGAs) increases, they are being increasingly used to implement large arithmetic-intensive applications. Large arithmetic intensive applications often contain a large proportion of datapath circuits. Since datapath circuits are designed to process multiple-bit-wide data, FPGAs implementing these circuits often have to transport a large amount of multiple-bit-wide signals from one computing element (such as a logic block, a DSP block, or a multi-bit addressable memory cell) to another. In this work, we investigate the area efficiency of FPGA routing resources for transporting multiple-bit-wide signals. It is shown that, for datapath circuits, the switch patterns used by the conventional routing architecture, which uniformly distribute routing switches across the routing tracks, are inefficient for connecting the computing elements to their tracks. The more efficient multi-bit aware patterns, which contain a densely populated single-bit region and a sparsely populated multi-bit region, can be effectively used to reduce the routing area of FPGAs for implementing arithmetic intensive applications by 6%–10%. It is also shown that the further sharing of configuration memory among the switches within the multi-bit aware patterns does not significantly increase their area efficiency since datapath circuits typically contain a mixture of multi-bit and single-bit signals—while configuration memory sharing can substantially increase the area efficiency of routing resources for transporting multi-bit signals, it also significantly reduces their ability for transporting single-bit signals. More importantly, configuration memory sharing can significantly reduce the effectiveness of the enhanced multi-bit aware patterns—patterns that incorporate both multi-bit aware and single-bit oriented switches within a single region in order to increase its ability for transporting both single-bit and multi-bit s-n-nignals.
机译:随着现场可编程门阵列(FPGA)的逻辑容量的增加,它们越来越多地用于实现大型算术密集型应用。大型算术密集型应用程序通常包含很大比例的数据路径电路。由于数据路径电路被设计为处理多位宽数据,因此实现这些电路的FPGA通常必须从一个计算元件(例如逻辑块,DSP模块或多路运算器)传输大量的多位宽信号。位可寻址存储单元)。在这项工作中,我们研究了用于传输多位宽信号的FPGA路由资源的区域效率。示出了,对于数据路径电路,由常规路由架构使用的,将路由开关均匀地分布在路由轨道上的开关模式对于将计算元件连接到它们的轨道是无效的。包含密集的单个位区域和稀疏的多位区域的更有效的多位感知模式可以有效地减少用于实现算术密集型应用的FPGA的路由区域,减少6%–10%。还显示出,由于数据路径电路通常包含多位和单位信号的混合,因此在多位感知模式内的交换机之间进一步共享配置存储器并不会显着提高其区域效率,而配置存储器共享可以实质上提高了用于传输多位信号的路由资源的区域效率,也大大降低了其传输单位信号的能力。更重要的是,配置内存共享会大大降低增强型多位感知模式的有效性,这种模式在单个区域内合并了多位感知和面向单个位的交换机,以提高其传输两个位的能力。和多位sn-nignals。

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