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Resource-Efficient FPGA Architecture and Implementation of Hough Transform

机译:资源高效的FPGA架构和Hough变换的实现

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Hough transform is widely used for detecting straight lines in an image, but it involves huge computations. For embedded application, field-programmable gate arrays are one of the most used hardware accelerators to achieve real-time implementation of Hough transform. In this paper, we present a resource-efficient architecture and implementation of Hough transform on an FPGA. The incrementing property of Hough transform is described and used to reduce the resource requirement. In order to facilitate parallelism, we divide the image into blocks and apply the incrementing property to pixels within a block and between blocks. Moreover, the locality of Hough transform is analyzed to reduce the memory access. The proposed architecture is implement on an Altera EP2S180F1508C3 device and can operate at a maximum frequency of 200 MHz. It could compute the Hough transform of 512 $times$ 512 test images with 180 orientations in 2.07–3.16 ms without using many FPGA resources (i.e., one could achieve the performance by adopting a low-cost low-end FPGA).
机译:霍夫变换被广泛用于检测图像中的直线,但是它涉及大量的计算。对于嵌入式应用,现场可编程门阵列是实现霍夫变换实时实现的最常用的硬件加速器之一。在本文中,我们提出了一种资源高效的架构,并在FPGA上实现了霍夫变换。描述了霍夫变换的增量性质,并将其用于减少资源需求。为了促进并行性,我们将图像划分为多个块,并将递增属性应用于块内以及块之间的像素。此外,分析了霍夫变换的局部性以减少存储器访问。所提出的架构在Altera EP2S180F1508C3器件上实现,并且可以在200 MHz的最大频率下运行。它可以在不使用大量FPGA资源的情况下,在2.07-3.16毫秒内计算512个x 512幅具有180个方向的测试图像的Hough变换(即,可以通过采用低成本低端FPGA来实现性能)。

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