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Independently-Controlled-Gate FinFET Schmitt Trigger Sub-Threshold SRAMs

机译:独立控制门FinFET施密特触发器亚阈值SRAM

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In this work, we propose three novel independently-controlled-gate Schmitt Trigger (IG_ST) FinFET SRAM cells for sub-threshold operation. The proposed IG_ST 8 T SRAM cells utilize split-gate FinFET devices with the front-gate devices serving as the stacking devices, and the back-gate devices serving as the intermediate node conditioning devices to provide built-in feedback mechanism for Schmitt Trigger action, thus reducing the cell transistor count/area and achieving improved static noise margin (SNM) and better tolerance to process variation and random variations. 3-D mixed-mode simulations are used to evaluate the Read static noise margin (RSNM), Write static noise margin (WSNM), hold static noise margin (HSNM), and Standby leakage of proposed cells, and results are compared with the standard 6 T cells and previously reported 10 T Schmitt Trigger sub-threshold SRAM cells. Compared with the conventional tied-gate 6 T cell, the proposed IG_ST SRAM cells demonstrate 1.81X and 2.11X higher nominal RSNM at $V_{CS}=$ 0.4 and 0.15 V, respectively. The cell layouts and areas are assessed based on scaled ground rules from 32 nm node, and the density advantage over previously reported 10 T Schmitt Trigger sub-threshold SRAM cells are illustrated. The cell AC performance (Read access time, Write time, and Read access time versus the number of cells per bit-line considering worst-case data pattern for bit-line leakage) and temperature dependence are evaluated, and shown to be adequate for the intended sub-threshold applications. Compared with previously reported 10 T Schmitt Trigger sub-threshold SRAM cells, the proposed cells exhibit comparable or better RSNM, higher density, and lower Standby leakage current. 3-D mixed-mode Monte Carlo simulations are performed to investigate the impacts of process variations ($L_{rm eff}$, $rm EOT$, $W_{rm fin}$, and $H_{rm fin}$) and random variations (Gate LER and Fin LER) on RSNM, WSNM, and HSNM. Our results indicate that even at the worst corner, two of the proposed cells can provide sufficient margin of $mu/sigma$ ratio.
机译:在这项工作中,我们针对亚阈值操作提出了三种新颖的独立控制门施密特触发器(IG_ST)FinFET SRAM单元。提出的IG_ST 8 T SRAM单元利用分裂栅FinFET器件,其中前栅器件用作堆叠器件,后栅器件用作中间节点调节器件,以为施密特触发器动作提供内置反馈机制,因此,减少了单元晶体管的数量/面积并获得了改善的静态噪声容限(SNM),并更好地容忍了工艺变化和随机变化。 3-D混合模式仿真用于评估拟建单元的读取静态噪声容限(RSNM),写入静态噪声容限(WSNM),保持静态噪声容限(HSNM)和待机泄漏,并将结果与​​标准电池进行比较6 T单元和先前报告的10 T Schmitt Trigger亚阈值SRAM单元。与常规的栓式栅极6 T单元相比,建议的IG_ST SRAM单元在$ V_ {CS} = $ 0.4和0.15 V时分别显示出更高的标称RSNM 1.81倍和2.11倍。基于来自32 nm节点的缩放接地规则评估了单元布局和面积,并说明了相对于先前报道的10 T Schmitt Trigger亚阈值SRAM单元的密度优势。评估了电池的交流电性能(读取访问时间,写入时间和读取访问时间与每位线的单元数(考虑到最坏情况的数据模式,以了解位线泄漏))和温度相关性,并显示出对电池的适应性预期的亚阈值应用。与先前报道的10 T施密特触发器亚阈值SRAM单元相比,拟议中的单元具有可比或更好的RSNM,更高的密度和更低的待机漏电流。执行3-D混合模式蒙特卡洛模拟以研究过程变化($ L_ {rm eff} $,$ rm EOT $,$ W_ {rm fin} $和$ H_ {rm fin} $)的影响。 RSNM,WSNM和HSNM上的随机变化(门LER和Fin LER)。我们的结果表明,即使在最差的拐角处,两个建议的单元也可以提供足够的$ mu / sigma $比率余量。

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