Device for reading memory cells of SRAM type, comprises output precharge circuit and Schmitt trigger circuit, for improved reading speed

摘要

The device comprises a differential amplifier with inputs (e1,e2) connected to the bit lines of a memory cell (Cmem) and a reference cell (Cref), respectively, a circuit for precharging the output of the differential amplifier to a predetermined voltage level (V1) which is intermediate between the high logic level and the low logic level, and a Schmitt trigger circuit, which is an inverter with a threshold, delivering the output signal DATAOUT. The intermediate voltage level corresponds to the means of high and low logic levels, which is (Vdd/2). The output precharge circuit comprises an upper branch with two p-MOS transistors and a lower branch with two n-MOS transistors; each branch comprises a transistor connected as a diode and a transistor controlled by a precharge signal. The device also comprises an equilibration circuit for equilibrating the two inputs (e1,e2) of the differential amplifier, which is activated in the precharge phase. The output precharge circuit is deactivated after the equilibration circuit. An integrated circuit comprises the device for reading memory cells, which are of SRAM type.