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Test Patterns of Multiple SIC Vectors: Theory and Application in BIST Schemes

机译:多个SIC向量的测试模式:理论和在BIST方案中的应用

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This paper proposes a novel test pattern generator (TPG) for built-in self-test. Our method generates multiple single-input change (MSIC) vectors in a pattern, i.e., each vector applied to a scan chain is an SIC vector. A reconfigurable Johnson counter and a scalable SIC counter are developed to generate a class of minimum transition sequences. The proposed TPG is flexible to both the test-per-clock and the test-per-scan schemes. A theory is also developed to represent and analyze the sequences and to extract a class of MSIC sequences. Analysis results show that the produced MSIC sequences have the favorable features of uniform distribution and low input transition density. The performances of the designed TPGs and the circuits under test with 45 nm are evaluated. Simulation results with ISCAS benchmarks demonstrate that MSIC can save test power and impose no more than 7.5% overhead for a scan design. It also achieves the target fault coverage without increasing the test length.
机译:本文提出了一种用于内置自检的新型测试模式生成器(TPG)。我们的方法以一种模式生成多个单输入更改(MSIC)向量,即,应用于扫描链的每个向量都是一个SIC向量。开发了可重配置的Johnson计数器和可伸缩SIC计数器,以生成一类最小转换序列。拟议的TPG对于按时钟测试和按扫描测试方案都是灵活的。还开发了一种理论来表示和分析序列并提取一类MSIC序列。分析结果表明,所产生的MSIC序列具有分布均匀,输入过渡密度低的良好特征。评估了设计的TPG和45 nm测试电路的性能。使用ISCAS基准测试的仿真结果表明,MSIC可以节省测试功率,并且对扫描设计的开销不会超过7.5%。它还可以在不增加测试时间的情况下达到目标故障范围。

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