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A Variation Tolerant Current-Mode Signaling Scheme for On-Chip Interconnects

机译:片上互连的耐变化电流模式信令方案

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Current-mode signaling (CMS) with dynamic overdriving is one of the most promising scheme for high-speed low-power communication over long on-chip interconnects. However, they are sensitive to parameter variations due to reduced voltage swings on the line. In this paper, we propose a variation tolerant dynamic overdriving CMS scheme. The proposed CMS scheme and a competing CMS scheme (CMS-Fb) are fabricated in 180-nm CMOS technology. Measurement results show that the proposed scheme offers 34% reduction in energy/bit and 42% reduction in energy-delay-product over CMS-Fb scheme for a 10 mm line operating at 0.64 Gbps of data rate. Simulations indicate that the proposed CMS scheme consumes 0.297 pJ/bit for data transfer over the 10 mm line at 2.63 Gb/s. Measurements indicate that the delay of CMS-Fb becomes 2.5 times its nominal value in the presence of intra-die variations whereas the delay of the proposed scheme changes by only 5% for the same amount of intra-die variations. Measurement and simulation results show that both the schemes are robust against inter-die variations. Experiments and simulations also indicate that the proposed CMS scheme is more robust against practical variations in supply and temperature as compared to CMS-Fb scheme.
机译:具有动态过驱动功能的电流模式信令(CMS)是通过长片上互连实现高速低功耗通信的最有希望的方案之一。但是,由于线路上的电压摆幅减小,它们对参数变化很敏感。在本文中,我们提出了一种耐变化的动态过驱动CMS方案。拟议的CMS方案和竞争CMS方案(CMS-Fb)是在180 nm CMOS技术中制造的。测量结果表明,对于以0.64 Gbps数据速率运行的10 mm线路,与CMS-Fb方案相比,该方案可将能耗/位降低34%,将能量延迟乘积降低42%。仿真表明,提出的CMS方案以2.63 Gb / s的速率通过10 mm线路传输数据时消耗0.297 pJ / bit。测量结果表明,在存在管芯内部变化的情况下,CMS-Fb的延迟变为其标称值的2.5倍,而对于相同量的管芯内部变化,所提出方案的延迟仅变化5%。测量和仿真结果表明,这两种方案均能抵抗管芯间的变化。实验和仿真结果还表明,与CMS-Fb方案相比,所提出的CMS方案在电源和温度的实际变化方面更具鲁棒性。

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