首页> 外文期刊>Very Large Scale Integration (VLSI) Systems, IEEE Transactions on >Multiple-Vote Symbol-Flipping Decoder for Nonbinary LDPC Codes
【24h】

Multiple-Vote Symbol-Flipping Decoder for Nonbinary LDPC Codes

机译:非二进制LDPC码的多表决符号翻转解码器

获取原文
获取原文并翻译 | 示例

摘要

A multiple-vote symbol-flipping (MV-SF) decoding algorithm for nonbinary low-density parity-check (NB-LDPC) codes is proposed in this paper. Our algorithm improves the generalized bit-flipping algorithm (GBFDA) by considering the multiplicity of the candidates at the check-node output, to perform a more accurate symbol-flipping decision at the variable node update. The MV-SF algorithm greatly improves the frame error rate performance of GBFDA and approaches the performance of the best state-of-the-art decoders [extended min-sum and min-max (Min–Max)] with lower complexity. For a NB-LDPC code over GF(32), the decoder derived from the proposed algorithm can reach a throughput higher than 500 Mb/s and a coding gain of 0.44 dB compared with the most efficient GBFDA architecture with only twice the silicon area. Our architecture has 27% efficiency gain compared with the best Min–Max architecture found in the literature, with a performance loss of just 0.21 dB at frame error rate .
机译:提出了一种用于非二进制低密度奇偶校验(NB-LDPC)码的多投票符号翻转(MV-SF)解码算法。我们的算法通过考虑校验节点输出处候选的多样性,改进了通用位翻转算法(GBFDA),以便在变量节点更新时执行更准确的符号翻转决策。 MV-SF算法极大地提高了GBFDA的帧错误率性能,并以较低的复杂度接近了最佳的最新解码器的性能[扩展的最小和和最小-最大(Min-Max)]。对于GF(32)上的NB-LDPC码,与仅使用硅面积两倍的最有效的GBFDA架构相比,从所提出的算法派生的解码器可以达到高于500 Mb / s的吞吐量和0.44 dB的编码增益。与文献中发现的最佳Min-Max架构相比,我们的架构的效率提高了27%,在帧错误率下的性能损失仅为0.21 dB。

著录项

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号