Experimental Validation of a Two-Phase Clock Scheme for Fine-Grained Pipelined Circuits Based on Monostable to Bistable Logic Elements

摘要

Research on fine-grained pipelines can be a way to obtain high-performance applications. Monostable to bistable (MOBILE) gates are very suitable for implementing gate-level pipelines, which can be achieved without resorting to memory elements. The MOBILE operating principle is implemented operating two series connected negative differential resistance devices with a clock bias. This brief describes and experimentally validates a two-phase clock scheme for such MOBILE-based ultragrained pipelines. Its advantages over other reported interconnection schemes for MOBILE gates, and also over pure CMOS two-phase counterparts, are stated and analyzed. Chains of MOBILE gates have been fabricated and the experimental results of their correct operation with a two-phase clock scheme are provided. As far as we know, this is the first working MOBILE circuit to have been reported with this interconnection architecture.