1.2-V Analog Interface for a 300-MSps HD Video Digitizer in Core 65-nm CMOS

摘要

This paper describes the front-end of a fully integrated analog interface for 300 MSps, high-definition video digitizers in a system on-chip environment. The analog interface is implemented in a 1.2 V, 65-nm digital CMOS process and the design minimizes the number of power domains using core transistors only. Each analog video receiver channel contains an integrated multiplexer with a current-mode dc-clamp, a programmable gain amplifier (PGA) and a pseudo second-order RC low-pass filter. The digital charge-pump clamp is integrated with low-voltage bootstrapped tee-switches inside the multiplexer, while restoring the dc component of ac-coupled inputs. The PGA contains a four-stage fully symmetric pseudo-differential amplifier with common-mode feedforward and inherent common-mode feedback, utilized in a closed loop capacitive feedback configuration. The amplifier features offset cancellation during the horizontal blanking. The video interface is evaluated using a unique test signal over a range of video formats for ${rm INL}{+}/{rm DNL}+$, ${rm INL}{-}/{rm DNL}-$. The 0.07–0.39 mV INL, 2–70 $mu{rm V}$ DNL, and 66–74 dB of SFDR, enable us to target various formats for 9–12 bit Low-voltage digitizers.