首页> 外文期刊>Very Large Scale Integration (VLSI) Systems, IEEE Transactions on >An src='/images/tex/29719.gif' alt='80times '> Analog-Implemented Time-Difference Amplifier for Delay-Line-Based Coarse-Fine Time-to-Digital Converters in 0.18- src='/images/tex/21769.gif' alt='mu '> m CMOS
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An src='/images/tex/29719.gif' alt='80times '> Analog-Implemented Time-Difference Amplifier for Delay-Line-Based Coarse-Fine Time-to-Digital Converters in 0.18- src='/images/tex/21769.gif' alt='mu '> m CMOS

机译: src =“ / images / tex / 29719.gif” alt =“ 80times”> 基于延迟线的粗略精细时间的模拟实现时差放大器0.18- src =“ / images / tex / 21769.gif” alt =“ mu”> m CMOS的数字转换器

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摘要

An analog-implemented time-difference amplifier applied for coarse-fine time-to-digital converters is presented in this paper. Implemented in 0.18-m CMOS process, a time difference within 225 ps can be amplified linearly under maximum frequency of 25 MHz. Measured maximum gain error is 4.1%. Measured output rms jitter is 84.5 ps under gain of . The time amplifier consumes 1.7 mW under supply voltage of 1.8 V.
机译:本文介绍了一种适用于粗细时间数字转换器的模拟实现的时差放大器。采用0.18-m CMOS工艺实现,可以在最大25 MHz的频率下线性放大225 ps内的时间差。测得的最大增益误差为4.1%。在增益为的情况下,测得的输出均方根抖动为84.5 ps。时间放大器在1.8 V的电源电压下消耗1.7 mW。

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