首页> 外文期刊>IEEE transactions on very large scale integration (VLSI) systems >Built-In Self-Test Methodology With Statistical Analysis for Electrical Diagnosis of Wearout in a Static Random Access Memory Array
【24h】

Built-In Self-Test Methodology With Statistical Analysis for Electrical Diagnosis of Wearout in a Static Random Access Memory Array

机译:内置自测方法和统计分析,用于静态随机存取存储器阵列中的电损耗诊断

获取原文
获取原文并翻译 | 示例

摘要

We present an electrical diagnosis methodology for a variety of wearout mechanisms, including back-end time-dependent dielectric breakdown (TDDB), electromigration, stress-induced voiding, gate oxide TDDB, and bias temperature instability, in an SRAM array. First, the built-in self-test (BIST) system detects wearout and identifies the locations of the faulty cells. Next, the physical location of the failure sites within SRAM cells is determined. There are some fault sites for different mechanisms which result in exactly the same electrical failure signature. For these faulty sites, the cause of failure probabilities for each wearout mechanism is estimated by matching the observed failure rate from BIST and the failure rate distribution computed by simulation and as a function of circuit use scenarios. The estimation of wearout distributions is helpful in determining the wearout limiting mechanisms in the field.
机译:我们为SRAM阵列中的各种磨损机制(包括后端时间相关的介电击穿(TDDB),电迁移,应力引起的空洞,栅极氧化物TDDB和偏置温度不稳定性)提出了一种电气诊断方法。首先,内置的自检(BIST)系统检测磨损并确定故障单元的位置。接下来,确定SRAM单元内故障部位的物理位置。不同机制存在一些故障点,这些故障点会导致完全相同的电气故障征兆。对于这些故障点,通过匹配从BIST观察到的故障率和通过仿真计算出的故障率分布,并根据电路使用场景来估计每种磨损机制的故障概率的原因。磨损分布的估计有助于确定现场的磨损限制机制。

著录项

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号