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A Low-Power Robust Easily Cascaded PentaMTJ-Based Combinational and Sequential Circuits

机译:低功耗,易于级联的基于PentaMTJ的组合电路和时序电路

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Advanced computing systems embed spintronic devices to improve the leakage performance of conventional CMOS systems. High speed, low power, and infinite endurance are important properties of magnetic tunnel junction (MTJ), a spintronic device, which assures its use in memories and logic circuits. This paper presents a PentaMTJ-based logic gate, which provides easy cascading, self-referencing, less voltage headroom problem in precharge sense amplifier and low area overhead contrary to existing MTJ-based gates. PentaMTJ is used here because it provides guaranteed disturbance free reading and increased tolerance to process variations along with compatibility with CMOS process. The logic gate is validated by simulation at the 45-nm technology node using a VerilogA model of the PentaMTJ.
机译:先进的计算系统嵌入了自旋电子设备,以改善常规CMOS系统的泄漏性能。高速,低功耗和无限的耐久性是自旋电子器件磁性隧道结(MTJ)的重要特性,可确保其在存储器和逻辑电路中的使用。本文介绍了一种基于PentaMTJ的逻辑门,与现有的基于MTJ的门相反,该逻辑门易于级联,自参考,预充电感测放大器中的电压裕量问题少,面积开销小。之所以使用PentaMTJ,是因为它提供了无干扰的读取保证,并提高了对工艺变化的容忍度,并且与CMOS工艺兼容。通过使用PentaMTJ的VerilogA模型在45纳米技术节点上进行仿真,可以验证逻辑门。

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