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STT-RAM Energy Reduction Using Self-Referenced Differential Write Termination Technique

机译:使用自参考差分写终止技术降低STT-RAM能量

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Spin-transfer torque random access memory (STT-RAM) has emerged as an attractive candidate for future nonvolatile memories. It advantages the benefits of current state-of-the-art memories including high-speed read operation (of static RAM), high density (of dynamic RAM), and nonvolatility (of flash memories). However, the write operation in the 1T-1MTJ STT-RAM bitcell is asymmetric and stochastic, which leads to high energy consumption and long latency. In this paper, a new write assist technique is proposed to terminate the write operation immediately after switching takes place in the magnetic tunneling junction (MTJ). As a result, both the write time and write energy consumption of 1T-1MTJ bitcells improves. Moreover, the proposed write assist technique leads to an error-free write operation. The simulation results using a 65-nm CMOS access transistor and a 40-nm MTJ technology confirm that the proposed write assist technique results in three orders of magnitude improvement in bit error rate compared with the best existing techniques. Moreover, the proposed write assist technique leads to 81% energy saving compared with a cell without write assist and adds only 9.6% area overhead to a 16-kbit STT-RAM array.
机译:自旋传递扭矩随机存取存储器(STT-RAM)已经成为未来的非易失性存储器的有吸引力的候选者。它利用了当前最先进的存储器的优势,包括(静态RAM的)高速读取操作,(动态RAM的)高密度和(闪存的)非易失性。但是,1T-1MTJ STT-RAM位单元中的写操作是不对称且随机的,这导致高能耗和长等待时间。在本文中,提出了一种新的写辅助技术,该技术可在磁隧道结(MTJ)中发生切换后立即终止写操作。结果,1T-1MTJ位单元的写入时间和写入能量消耗均得到改善。此外,提出的写辅助技术导致无错误的写操作。使用65纳米CMOS存取晶体管和40纳米MTJ技术的仿真结果证实,与现有最佳技术相比,拟议的写辅助技术可将误码率提高三个数量级。此外,与没有写辅助功能的单元相比,拟议的写辅助技术可节省81%的能源,并且对16 kb STT-RAM阵列仅增加9.6%的面积开销。

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