Gate Field Engineering and Source/Drain Diffusion Engineering for High-Performance Si Wire GAA MOSFET and Low-Power Strategy in Sub-30-nm-Channel Regime

摘要

This paper reconsiders the design methodology of the short-channel gate-all-around (GAA) SOI MOSFET and proposes an advanced method for enhancing its performance. The new ideas are based on gate field engineering and source and drain diffusion engineering. The validity of the proposal is demonstrated by device simulations. Covering the junction of a Si wire body with a relatively thick gate insulator raises the carrier density of low-doped source and drain diffusions, resulting in a drastic reduction in parasitic resistance (which has, up to now, hindered performance enhancement) as well as the suppression of short-channel effects due to the effective extension of channel length; it is also demonstrated that this improvement can be expected even in cases of narrow highly-doped source and drain diffusion regions with abrupt junctions. The simulation results suggest that 15-nm- and 20-nm-channel GAA SOI MOSFET's with abrupt junctions will be useful with a device with a body cross-section of 10 nm × 10 nm and a thick insulator covering the junction. On the other hand, it is demonstrated that the proposed GAA device must have long and graduated source and drain diffusion regions in order to achieve the expected one-order lower-standby power; a loss of drivability has to be accepted. In addition, it is shown that drivability can be improved by slightly expanding the cross-section of source and drain diffusion regions without seriously impacting the area penalty.