Highly efficient PWM synchronous buck converter with optimized LDMOS

摘要

In this work, a design of high efficiency synchronous buck converter with an optimized LDMOS is presented which works in VHF frequency domain. The circuit performance of the buck converter is then analyzed and optimized to increase the efficiency and to reduce the power losses without modifying the circuit. The analysis and optimization is performed by varying the different device parameters like drift region doping concentration (D_(Drift)) and drift region length (L_(Drift)) along with the circuit level parameters like the dead time and the switching frequency. The effect of the parameters is found to reduce the power losses of the circuit. The circuit with optimized parameters yields 80% efficiency at 100 MHz switching frequency.