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Ferroelectric Schottky barrier tunnel FET with gate-drain underlap: Proposal and investigation

机译:具有栅-漏重叠的铁电肖特基势垒隧道FET:建议和研究

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In this paper, for the first time, a novel ferroelectric schottky barrier tunnel FET (Fe SB-TFET) is proposed and investigated. The Fe SB-TFET consists of ferroelectric gate stack with highly doped pocket at the source/drain and channel interface. In addition, for the suppression of ambipolar leakage current (I_(AMB)), gate-drain underlap is employed. By using ferroelectric gate stack, we effectively amplified the applied gate voltage to enhance electric field for the reduction of tunneling barrier width at the source side schottky barrier. As a result, the increased tunneling probability improves the device performance in terms of high I_(ON). high W_(OFF) ratio, reduced I_(AMB) and low subthreshold swing (SS) as compared to the conventional SB-TFET having double pocket We also investigate the influence of highly doped pocket (HDP) doping concentration and length on the device performance.
机译:本文首次提出并研究了一种新型的铁电肖特基势垒隧道FET(Fe SB-TFET)。 Fe SB-TFET由铁电栅极叠层组成,在源极/漏极和沟道界面处具有高度掺杂的凹穴。另外,为了抑制双极性泄漏电流(I_(AMB)),采用了栅极-漏极下重叠。通过使用铁电栅叠层,我们有效地放大了施加的栅极电压以增强电场,以减小源极侧肖特基势垒的隧穿势垒宽度。结果,增加的隧穿概率就高I_(ON)而言改善了器件性能。与具有双口袋的常规SB-TFET相比,具有较高的W_(OFF)比,降低的I_(AMB)和较低的亚阈值摆幅(SS)我们还研究了高掺杂口袋(HDP)掺杂浓度和长度对器件性能的影响。

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