A 220-mm2, four- and eight-bank, 256-Mb SDRAM withsingle-sided stitched WL architecture

摘要

A 220-mm2, 256-Mb SDRAM has been fabricated in fullynplanarized 0.22-Μm CMOS technology with buried strap trench cell. Thensingle-sided stitched word-line (WL) architecture employs asymmetricnblock activation and shared row decoders to realize 86.7%ncell/chip-length efficiency (57.3% cell/chip efficiency). A staggered WLndriver arrangement makes it possible to build the drivers on an0.484-Μm WL pitch in limited space. An intraunit address incrementnpipeline scheme having two logical 8-Mb arrays within one physical 16-Mbnunit results in a burst frequency up to 200 MHz for single data rate,nwhile allowing four- and eight-bank organizations. A data rate of 270nMbits/s was confirmed with a 135-MHz frequency doubling test mode.nSingle-ended addresses and a single ended read-write-drive bus reducenthe ICC4 current to ~90 mA for 100-MHz seamless burstnoperation. A detailed shmoo analysis demonstrates address-access time ofn13.5 ns and clock-access time of 5 ns. This design also uses anselectable row domain and divided column redundancy scheme that repairsnup to ~1400 faults/chip with only 8% chip overhead