Low-power clock-deskew buffer for high-speed digital circuits

摘要

An IC containing four clock deskew buffers using thendelay-locked-loop technology has been fabricated in a 0.6 Μm singlenpoly double metal CMOS process. The core chip area is 0.9×0.9 mmn2. The maximum operating frequency is 80 MHz, and the totalnpower dissipation of the four deskew buffers is 59 mW for a 3 V supplynvoltage. The maximum clock skew after deskewing is less than 300 ps, andnthe peak-to-peak clock jitter is less than 170 ps. The deskew range isn0.5-3.8 ns