The circuit features a charge-buffered coupling between the common-emitter node of the switching transistors and the base of an active-pull-down npn transistor. This coupling scheme provides a much larger dynamic current than that which can be reasonably achieved through the capacitor coupling and a DC path to alleviate the AC-testing requirement. Furthermore, the dynamic current is utilized effectively by the logic stage, thus allowing a reduction in the power consumption of the logic stage without sacrificing the switching speed. Based on an 0.8- mu m double-poly self-aligned bipolar technology at a power consumption of 1.0 mW/gate, the circuit offers 37% improvement in both the speed and load driving capability for a loaded gate compared with the conventional ECL circuit. The design and scaling considerations of the circuit are discussed.
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