Combinational logic approach for implementing an improvedapproximate squaring function

摘要

The Viterbi algorithm is a fundamental signal-processing techniquenused in different communication systems. An improved, implemented, andntested approximate squaring function for the Viterbi algorithm isnintroduced in this paper. The implementation of this improved squaringnfunction is based on combinational logic design. The performance of thisnnew approach has been verified by implementing a 7-bit squaring functionnchip in a 2-Μm CMOS technology. The active integrated circuit area ofnthe chip was 380×400 Μm2, and the delays throughnthis area were 5.7 and 3.0 ns for rising and falling edges,nrespectively. Compared with a previous design, this approach reducesnerror associated with approximation, simplifies the complexity ofnrealization, reduces the integrated circuit area by at least 40%, andnincreases the speed by about 100%