Combinational logic circuits implemented with inverter function logic

摘要

Combinational logic circuits are implemented with Inverter Function Logic gates. Such circuits may utilize the logical complement of an input signal in the logical operation performed by the gate without having to use a separate inverter stage or a dual level Cascode arrangement. If such circuits employ the feature of collector dotting, diode clamps are not required. Combinational logic circuits fabricated with Inverter Function Logic utilize a level shifted transistor means in lieu of the standard reference transistor of ECL gates so that input voltages are compared with each other rather than with a reference voltage. In one embodiment the level shifted transistor means comprises a transistor having a level shifted representation of an input signal whose complement is to be used in the logical operation applied to its base. In another embodiment the level shifted transistor means comprises a transistor having a Schottky diode connected between its emitter and the common emitter connection of the input transistors.