VLSI design and implementation of an improved squaring circuit by combinational logic

摘要

An improved VLSI squaring circuit, for a Viterbi algorithm, is designed and implemented in the n-well CMOS 2/spl mu/m process. It is faster and more area efficient than conventional and table look-up approaches. In addition it compensates for inaccuracies and noise. The new design is based on combinational logic and the implemented chip reduces the IC area by more than 40% and increases the speed by 100%, as compared to other published designs (Eshraghi et al., 1994). Design considerations, performance evaluations, and test results are presented.