Design of a 3-V 300-MHz low-power 8-b×8-b pipelinedmultiplier using pulse-triggered TSPC flip-flops

摘要

This paper describes the design of a low-power pipelinednmultiplier. It is illustrated in this paper that the power consumptionnof the clocking system cannot be overlooked and the design of thenstorage element is the key to low power. A new pulse-triggered truensingle-phase clocking (TSPC) flip-flop (PTTFF) is proposed for thisnpurpose in this design. The PTTFF features true single-phase clocking,nsimple structure, and high performance. One PTTFF comprises only fiventransistors with only one controlled by the clock. Using the PTTFFntogether with the 14-transistor pseudo-NMOS full adder, an 8-b×8-bnpipelined multiplier has been designed and implemented, employing an0.6-Μm CMOS process. When the multiplier operates at the operatingnfrequency of 300 MHz with VDD equal to 3.3 V, it dissipates only 53% ofnthe power of the multiplier designed with nine-transistor TSPCnflip-flops under the same operating conditions. When the supply voltagenfor the core array is reduced to 2.5 V, the multiplier can still work upnto 300 MHz with only 47% of the power of the multiplier designed usingnthe S and D full adders and C2MOS latches with VDD equal ton3.3 V. The chip has been fabricated, and the measured power is 52.4 mWnwhen operated at 300 MHz and 3.3 V