Direct digital frequency synthesis of low-jitter clocks

摘要

This paper presents a new phase correction technique applicable tonphase accumulators that allows them to express arbitrary rational dividenratios such as R=N/M. Compared to existing methods, the technique givesnbetter results in terms of jitter, and it simplifies design andnimplementation of practical direct digital synthesis circuits. A typicalnapplication of the proposed technique is digital television, wherencombinations of existing standards lead to the need to synchronizenexactly a 6.144-MHz audio clock with a 35.46895-MHz video clock. Thisnimplies a divide ratio of R=122880/709379