VIDEO CLOCK SYNTHESIS SCHEME OF DISPLAYPORT RECEIVER USING DIRECT DIGITAL FREQUENCY SYNTHESIZER

摘要

A digital frequency synthesizer according to the present invention is a direct digital frequency synthesizer using at least a frequency ratio value, which refers to a ratio between a frequency of input clock and a frequency of output clock, for generating the output clock from the input clock. The present invention is characterized by comprising: a divider merged delta sigma modulator (10) for generating a dithered result of a integer part of the frequency ratio value and a decimal part of the frequency ratio value after receiving the frequency ratio value; an integer divider (20) for generating a middle clock from the input clock using the integer part, wherein the input clock is demultiplied corresponding to the integer part; a fractional divider (30) for generating the output clock from the middle clock using the decimal part, wherein the edge of the middle clock is shifted corresponding to the decimal part. According to the present invention, a frequency wanted can be easily synthesized in the case of synthesizing a frequency using remarkably large values of M and N like a display port, a performance degradation problem caused by a low loop filter bandwidth and the like can be solved, and a frequency with a broad bandwidth can be generated.