A 2-V 900-MHz monolithic CMOS dual-loop frequency synthesizer forGSM receivers

摘要

A 900-MHz monolithic CMOS dual-loop frequency synthesizer suitablenfor GSM receivers is presented. Implemented in a 0.50-Μm CMOSntechnology and at a 2-V supply voltage, the dual-loop frequencynsynthesizer occupies a chip area of 2.64 mm2 and consumes anlow power of 34 mW. The measured phase noise of the synthesizer isn-121.8 dBc/Hz at 600-kHz offset, and the measured spurious levels aren-79.5 and -82.0 dBc at 1.6 and 11.3 MHz offset, respectively