Design of a very linear CMOS transconductance input stage for continuous-time filters

摘要

A CMOS differential input stage for transconductance amplifiers that combines a low noise excess factor, low input capacitance, and high common-mode rejection ratio with a very good linearity is described. The measured distortion is only 0.2% for a 1-V RMS input signal and only 1% for a 2-V RMS input signal on a test circuit implemented in a standard 3- mu m CMOS process, using +or-5-V supplies, resulting in over 85 dB of dynamic range. Applications include high-performance continuous-time filters and linear amplifiers.