Application specific CMOS output driver circuit design techniques to reduce simultaneous switching noise

摘要

Application specific CMOS circuit design techniques to reduce simultaneous switching noise (SSN-also known as Delta-I noise or ground bounce) were analyzed. Detailed investigation on the CMOS output driver switching current components was performed. The limitations in using current controlled (CC) CMOS output drivers in high-speed (<30 MHz) design applications are explained. Application specific, high-speed, controlled slew rate (CSR) CMOS output drivers were studied and designed. For a given device channel length, once the predriver and driver device sizes are fixed, the performance (speed, switching noise, sink/source capabilities) is determined. With controlled slew rate output drivers, more than 50% improvement was found in the input receiver noise immunity (measure of maximum tolerable SSN) compared to conventional drivers, while the speed and sink/source capabilities are preserved. This effective SSN reduction improvement is achieved with only a small increase in output driver silicon area. The CSR output driver uses distributed and weighted switching driver segments to control the output driver's slew rate for a given load-capacitance. These CSR CMOS output drivers were compared with standard CMOS output drivers, showing significant reduction in effective switching noise pulse width.