RTP-Grown Oxynitride Layers Meet Gate Challenges

摘要

Information technology's progress over the past decades has depended on the SiO_2/Si system's extremely high quality. One key application of this system is MOSFET gate dielectric. Until now, SiO_2 gate oxide played a critical role in device performance. As lateral MOSFET dimensions scale into the deep submicron regime (<100 nm), SiO_2-based gate dielectrics are reaching their limits. According to the 2003 International Technology Roadmap for Semiconductors, the 100 nm technology node requires the gate dielectric's equivalent oxide thickness (EOT) to have values of 0.9-1.4 nm for low-operating-power ASIC MOSFET devices. Direct tunneling currents through the SiO_2 gate oxide increase exponentially with decreasing oxide thickness. Another drawback related to gate di-electric thickness downscaling is the degradation of its barrier properties against the diffusion of dopants from heavily doped P+ polysilicon gates (boron penetration).