Wafer Edge Yield

摘要

With the scaling of 300mm production and the development of sub-90nm device technology, defect sources from the wafer's edge have become a major concern. The most demanding process integration challenges, due to increased device and stack complexity, frequently lead to defect control problems in this most difficult inspection area. Thin, fragile films produced with exotic dielectrics and other advanced materials cause difficulties when deposited over residues in the high stress wafer edge region.