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Variation of interface trap level charge density within the bandgap of 4H-SiC with varying oxide thickness

机译:4H-SiC带隙内界面陷阱能级电荷密度随氧化物厚度的变化

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摘要

Interfacial characteristics of metal oxide-silicon carbide (MOSiC) structure with different thickness of SiO2, thermally grown in steam ambient on Si-face of 4H-SiC (0 0 0 1) substrate were investigated. Variations in interface trapped level density (D it) was systematically studied employing high-low (H-L) frequency C–V method. It was found that the distribution of D it within the bandgap of 4H-SiC varied with oxide thickness. The calculated D it value near the midgap of 4H-SiC remained almost stable for all oxide thicknesses in the range of 109–1010 cm−2 eV−1. The D it near the conduction band edge had been found to be of the order of 1011 cm−2 eV−1 for thicker oxides and for thinner oxides D it was found to be the range of 1010 cm−2 eV−1. The process had direct relevance in the fabrication of MOS-based device structures.
机译:研究了在4H-SiC(0 0 0 1)衬底的Si面上在蒸汽环境中热生长的不同SiO2厚度的金属氧化物-碳化硅(MOSiC)结构的界面特性。利用高-低(C-V)频率法系统研究了界面俘获能级密度(D it )的变化。发现4H-SiC带隙中D it 的分布随氧化物厚度的变化而变化。对于在109 –1010 cm−2 eV-1 范围内的所有厚度的氧化物,在4H-SiC中带附近的计算出的D it 值几乎保持稳定。 sup>。对于较厚的氧化物和较薄的氧化物D it,已发现导带边缘附近的D it约为1011 cm−2 eV-1 。 / sub>的范围是1010 cm−2 eV-1 。该工艺与制造基于MOS的器件结构直接相关。

著录项

  • 来源
    《Pramana》 |2011年第1期|p.165-172|共8页
  • 作者单位

    Sensors and Nano-Technology Group, Semiconductor Devices Area, Central Electronics Engineering Research Institute (CEERI)/Council of Scientific and Industrial Research (CSIR), Pilani, 333 031, India;

    Center of Excellence in Material Sciences (Nanomaterials), Department of Applied Physics, Z.H. College of Engg. &amp Tech., Aligarh Muslim University, Aligarh, 202 002, India;

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  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类
  • 关键词

    4H-SiC; wet thermal oxidation; MOSiC structure; interface trap level density.; 85.30.-z; 81.05.-t; 72.20.-t;

    机译:4H-SiC;湿热氧化;MOSiC结构;界面陷阱能级密度;85.30.-z;81.05.-t;72.20.-t;

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