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Compile-time techniques for improving scalar access performance in parallel memories

机译:改善并行存储器中标量访问性能的编译时技术

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Compile-time techniques for storage allocation of scalar values into memory modules that limit run-time memory-access conflicts are presented. The allocation approach is applicable to those operands in instructions that can be predicted at compile-time, where an instruction is composed of the multiple operations and corresponding operands that execute in parallel. Algorithms to schedule data transfers among memory modules to avoid conflicts that cannot be eliminated by the distribution of values alone are developed. The techniques have been implemented as part of a compiler for a reconfigurable long instruction word architecture. Results of experiments are presented demonstrating that a very high percentage of memory access conflicts can be avoided by scheduling a very low number of data transfers.
机译:提出了将标量值存储分配到内存模块中的编译时技术,这些代码限制了运行时内存访问冲突。分配方法适用于可以在编译时预测的指令中的那些操作数,其中一条指令由多个操作和并行执行的相应操作数组成。开发了用于调度存储模块之间的数据传输以避免仅通过值的分配无法消除的冲突的算法。该技术已实现为可重配置长指令字体系结构的编译器的一部分。实验结果表明,通过计划非常少的数据传输,可以避免很大比例的内存访问冲突。

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