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Implementation of Pipelined FastICA on FPGA for Real-Time Blind Source Separation

机译:用于FPGA的实时FastICA流水线实时盲源分离

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Fast independent component analysis (FastICA) algorithm separates the independent sources from their mixtures by measuring non-Gaussian. FastICA is a common offline method to identify artifact and interference from their mixtures such as electroencephalogram (EEG), magnetoencephalography (MEG), and electrocardiogram (ECG). Therefore, it is valuable to implement FastICA for real-time signal processing. In this paper, the FastICA algorithm is implemented in a field-programmable gate array (FPGA), with the ability of real-time sequential mixed signals processing by the proposed pipelined FastICA architecture. Moreover, in order to increase the numbers precision, the hardware floating-point (FP) arithmetic units had been carried out in the hardware FastICA. In addition, the proposed pipeline FastICA provides the high sampling rate (192 kHz) capability by hand coding the hardware FastICA in hardware description language (HDL). To verify the features of the proposed hardware FastICA, simulations are first performed, then real-time signal processing experimental results are presented using the fabricated platform. Experimental results demonstrate the effectiveness of the presented hardware FastICA as expected.
机译:快速独立成分分析(FastICA)算法通过测量非高斯将独立来源与它们的混合物分开。 FastICA是一种常见的离线方法,可从其混合物中识别伪影和干扰,例如脑电图(EEG),脑磁图(MEG)和心电图(ECG)。因此,为实时信号处理实现FastICA非常有价值。在本文中,FastICA算法是在现场可编程门阵列(FPGA)中实现的,具有通过提出的流水线FastICA架构进行实时顺序混合信号处理的能力。此外,为了提高数字精度,已经在硬件FastICA中执行了硬件浮点(FP)运算单元。此外,建议的管道FastICA通过以硬件描述语言(HDL)手动编码硬件FastICA提供了高采样率(192 kHz)的能力。为了验证所提出的硬件FastICA的功能,首先进行了仿真,然后使用预制平台提供了实时信号处理实验结果。实验结果证明了所提出的硬件FastICA的有效性。

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