Field programmable array-based PCI interface for a coprocessor system

摘要

This paper presents the design and implementation of a field programmable gate array (FPGA)-based PCI bus interface for a general purpose parallel neurocomputer, which is hosted by a personal computer. The basic background of the PCI bus and a detailed discussion of applicable FPGA design considerations are given. With FPGA, critical implementation factors are the realization of fast-enough state machines and efficient resource allocation. Emphasis is placed on presenting how to allocate resources efficiently from the VHDL hardware description language. Related to the overall implementation. PCI bus agent initialization and configuration from the operating system are considered.