An efficient and scalable parallel mapping of pulse-Doppler radar signal processing chain on a multi-core DSP

摘要

Digital Pulse-Doppler radar chain consists of signal processing algorithms that require high computing power. Multi-processor and multi-core parallel embedded machines are one of the solutions to meet real-time constraints of many radar applications. In this paper, we proposed efficient and scalable parallelization methods of the PulseDoppler radar signal processing chain. First, we evaluated Open Multi Processing (OpenMP) to identify its best scheduling technique in order to exploit efficiently the available computing cores. Then, we have proposed new parallel and scalable approaches based on direct memory access (DMA) and inter-processor communication (IPC) techniques, combined with the best OpenMP scheduling method to accelerate radar signal processing chain. To prove the scalability of our proposed parallel approaches, two radar use cases with different real-time and memory constraints have been experienced. We used the eight cores C6678 digital signal processor (DSP) as a target for all our implementations. The obtained results show an overall parallel efficiency of 95%, which is better than the best state-of-the-art implementations.