Experimental verification of the effectiveness of a new circuit to mitigate single event upsets in a Xilinx Artix-7 field programmable gate array

摘要

A single event transient (SET) filtering technique for the Xilinx Artix-7 Field Programmable Gate Array (FPGA) is investigated experimentally. The technique combines AND - OR gate circuits to provide a single circuit that can dissipate SETs irrespective of whether the input state is high or low. It uses fewer resources than the widely used Triple Modular Redundancy (TMR) and significantly reduces event upsets in a FPGA.This paper presents the results of the experimental investigation, with the SET filter applied to various sequential circuit configurations, by proton beam irradiation. Their implementation and evaluation in-beam show their efficiency in eliminating SETs and single event upsets (SEU) compared to unmitigated designs.