Investigation of turbo decoding techniques based on lottery arbiter in 3D network on chip

摘要

In this digital age, turbo Codes have been largely favoured in various high speed wireless communication systems standards (3GPP-LTE, WiMAX and WiFi). These codes are preferred due to their high performance that corresponds to that of the Shannon limit. Due to the current trends in wireless communications, there has been a demand for high throughput and power efficiency leading to revolutionary research. The ASIP architecture, which is the multi-application specific instruction processor, has been extensively preferred for turbo decoders due to high-throughput and flexibility. The multi-ASIP turbo decoders are successfully brought forth by utilization of a network-on-chip (NoC) structure. This paper incorporates the study of the turbo decoding process, as well as analyzing the addressing patterns for various communication standards. To reduce the complexity of the NoC, mathematical calculation sequence and sub networking techniques are proposed. The arbitration of the network is done by lottery routing algorithm. The final results obtained from the structure proposed in this paper show a massive breakthrough compared to Network-on-chip (NoC). The results show a 50% improvement for High Speed Downlink Packet Access (HSDPA) and a breakthrough of 13% for Long Term Evolution (LTE) in throughput to area efficiency. (C) 2019 Published by Elsevier B.V.