Improvement of energy-efficiency in off-chip caches by selective prefetching

摘要

The line size/performance trade-offs in off-chip second-level caches in light of energy-efficiency are revisited. Based on a mix of applications representing severer and mobile computer system usage, we show that while the large line sizes(128 bytes)typically used maximize performance, they result in a high power dissipation owing to the limited exploitation of spatial locality. In contrast, small blocks (32 bytes)are found to cut the energy-delay by more than a factor of 2 with only a moderate performance loss of less than 25/100. As a remedy, prefetching, if applied selectively, is shown to avoid the performance losses of small blocks, yet keeping power consumption low.