Effectiveness of Caches and Data Prefetch Buffers in Large-Scale Shared Memory Multiprocessors

摘要

Large shared memory multiprocessors usually have difficulty in matching the memory speed with the processor speed due to the large interconnection network between processors and shared memory. In this thesis, we explore the effectiveness of caches and data prefetching by the processor in eliminating the memory access bottleneck. Using trace driven simulations of numerical subroutines that have been transformed into parallel form, we model the following multiprocessor characteristics in our performance evaluation, the cost of a cache coherence enforcement scheme, the effect of a high degree of overlap between cache miss service, the cost of a pin limited data path between shared memory and caches, the effect of a high degree of data prefetching, the program behavior of a scientific workload as represented by over 20 numerical subroutines, and the parallel execution of programs. The optimal cache block size is examined in detail and we found that a small cache block size is favored in the multiprocessors of interest. A compile-time cache coherence scheme that allows data to change cacheability is proposed and is shown to significantly perform better than schemes which do not allow cacheability changes. We show the relative effectiveness of caches and data prefetching for a range of network delays and bandwidths and propose techniques to overcome some of the performance degradations due to read/write access to shared memory. 47 refs., 40 figs., 8 tabs. (ERA citation 13:013829)