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Measuring the power efficiency of subthreshold FPGAs for implementing portable biomedical applications

机译:测量用于实现便携式生物医学应用的亚阈值FPGA的功率效率

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Power is a significant design constraint for implementing efficient portable biomedical applications. Operating transistors in the subthreshold region can significantly reduce power consumption; it, however, also reduces performance. While this performance reduction can be significant in many applications, the low frequency nature of biosignals makes subthreshold region a good candidate for implementing biomedical applications. In this work, we investigate the feasibility of designing a specialized FPGA for implementing portable biomedical applications. In particular, we perform a case study on the performance of the Burg algorithm, a widely used biomedical signal processing algorithm, to determine the minimum operating frequency required for the processing of biosignals in real time. Based on the requirement, the trade-off between power consumption and performance is measured for FPGA routing resources operating in the subthreshold region. It is found that operating FPGA routing resources in the subthreshold region can significantly reduce power consumption while allowing the Burg algorithm to operate in real time. For the 32 nm Predictive Technology Model studied in this work, we observed a power reduction of 197.7 times (which corresponds to a power-delay-product reduction of 10.78 times) for operating FPGA routing tracks in the subthreshold region under a supply voltage of 0.4 V. Under this voltage, the FPGA can operate at 2.0 MHz while allowing signals to propagate unregistered through 45 routing tracks. Furthermore, the 2.0 MHz operating frequency meets the real-time requirement of the Burg algorithm for processing 20,000 samples per second.
机译:功率是实现高效便携式生物医学应用程序的重要设计约束。在亚阈值区域内工作的晶体管可以显着降低功耗。但是,它也会降低性能。尽管这种性能下降在许多应用中可能是显着的,但生物信号的低频特性使亚阈值区域成为实现生物医学应用的理想选择。在这项工作中,我们研究了设计专用FPGA来实现便携式生物医学应用的可行性。特别是,我们对广泛使用的生物医学信号处理算法Burg算法的性能进行了案例研究,以确定实时处理生物信号所需的最低工作频率。根据要求,针对在亚阈值区域内运行的FPGA路由资源,在功耗和性能之间进行了权衡。发现在亚阈值区域中操作FPGA路由资源可以大大降低功耗,同时允许Burg算法实时运行。对于这项工作中研究的32 nm预测技术模型,我们观察到在电源电压为0.4的情况下,在亚阈值区域内运行FPGA布线轨迹时,功耗降低了197.7倍(相当于功率延迟乘积降低了10.78倍)。 V.在此电压下,FPGA可以在2.0 MHz的频率下工作,同时允许信号通过45个布线路径未经注册地传播。此外,2.0 MHz的工作频率满足Burg算法的实时要求,每秒可处理20,000个样本。

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