As the density of DRAM approaches giga-bit scaled DRAM, many critical challenges emerge from its small cell size. The most critical obstacles are insufficient cell capacitance and large leakage current at storage junction. Besides, variation of threshold voltage fo memory cell transistor and the increased delay of word line and bit line come up to limit performance of device. In this paper, the critical issues in giga-bit technology are reviewed and appropriate approaches to overcome these issues are discussed based on the technology generation. The discussions are mainly focused on the key technologies: memory cell capacitor technology, memory cell transistor technology, work line and bit line technology, memory cell connection technology and metallization technology. Down to the 0.10 μm technology generation, we can specifically define the challenges for each technology generation and can find the ways to overcome these obstacles with proper techology migratons based on the current Capaciton-Over-bit line cell structure. The technology migration will move toward Ta_2O_5 capacitor, modified memory cell transistor, W-gate, W-bit line and self-aligned landing pad technology in cost-effective ways. Beyond the 0.10μm technology generation, breakthrough technology seems to be indispensable. The breakthrough technology should happen in memory cell concept, memory cell structure and integration technology.
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