A voltage calibration technique of electro-optic probing for characterization internal to IC's chip

摘要

This paper simulates the electric potential distribution and the electro-optic (EO) signal amplitude in a longitudinal poled EO polymer external probe tip on the electric signal transmission lines under test. The influence of the circuit layout on the EO probing is discussed. A novel probing configuration with a poled polymer EO probe tip is built and demonstrated for the first time, by which the signal voltage level corresponding to the EO signal can be calibrated. Using the new probe tip, we examine the influence of the variations of the line-width and the spacing between neighboring lines on the EO signal. The results indicate that when the vertical distance between the tested point on the lines and the reference electrode is not larger than that between the tested point and its neighboring conductor, the disturbance from circuit layout can be avoided so that the voltage calibration of EO signal can be carried out.