A novel technique for duty cycle correction for reference clocks in frequency synthesizers

摘要

Frequency Multipliers to be used with Frequency Synthesizers require duty cycle of nearly 50% and low phase noise contribution to the overall system phase noise for proper operation. In this paper, we first analyze the impact of the imperfect duty cycle clocks on the overall synthesizer system performance, then propose a mixed signal solution based on the fact that the average DC value of a signal is proportional to its duty cycle. The solution uses a feedback loop for coarse and fine duty cycle correction resolution. Proposed duty cycle correction circuit can correct input duty cycle variations from 40% to 60% for a 40 MHz input frequency with 50% +/- 0.3% accuracy. Furthermore, in order to estimate the output clock phase noise, a simulation method with supply white noise model is proposed. The circuit is implemented in 65 nm UMC CMOS process. Operating from 1.2-V supply, the circuit only dissipates 0.26 mA.