DUTY CYCLE BETWEEN TWO REFERENCE CLOCKS IN A CLOSED LOOP PHASE ROTOR SUB SYSTEM, AN ORTHOGONAL RELATION, AND A DYNAMIC ORTHOGONAL CLOCK CORRECTION SYSTEM CAPABLE OF AUTOMATICALLY CORRECTING AN AMPLITUDE

摘要

PURPOSE: A duty cycle, an orthogonal relation, and a dynamic orthogonal clock correction system are provided to reduce a data sample clock jitter by compensating for a mismatch effect in a clock dividing circuit.;CONSTITUTION: At least two input signals including at least one in-phase clock and a single orthogonal clock is controlled. The adjusted orthogonal clock signal is applied to a device which generates a four-quadrant interpolated output clock phase. The interpolated output clock phase is delayed in order to form a clock for a measurement device. At least two adjusted input signal are measured in the range of the interpolated output clock phase. Errors regarding the in-phase clock and the orthogonal clock are determined by using the sampled information from the measurement device. By using the determined error information, the in-phase clock and the orthogonal clock are adapted to a closed loop feedback configuration. A signal measurement function part(157) includes an offset buffer, an offset DAC, and a determination latch.;COPYRIGHT KIPO 2011