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4.5-kV 20-mΩ.cm~2 Implantation-Free 4H-SiC BJT with Trench Structures on the Junction Termination Extension

机译:4.5kV20mΩ.cm〜2无注入4H-SiC BJT,在结终端扩展上具有沟槽结构

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摘要

A single-mask junction termination extension with trench structures is formed to realize a 4.5 kV implantation-free 4H-SiC bipolar junction transistor (BJT). The trench structures are formed on the base layer with dry etching using a single mask. The electric field distribution along the structure is controlled by the number and dimensions of the trenches. The electric field is distributed by the trench structures and thus the electric field crowding at the base and mesa edges is diminished. The design is optimized in terms of the depth, width, spacing, and number of the trenches to achieve a breakdown voltage (V_b) of 4.5 kV, which is 85% of the theoretical value. Higher efficiency is obtainable with finer lithographic resolution leading to smaller pitch, and higher number and narrower trenches. The specific on-resistance (R_(on)) of 20 mΩ.cm~2 is measured for the small-area BJT with active area of 0.04 mm2. The BV-R_(on) of the fabricated device is very close to the SiC limit and by far exceeds the best SiC MOSFETs.
机译:形成具有沟槽结构的单掩模结终端扩展,以实现4.5 kV免注入4H-SiC双极结晶体管(BJT)。使用单个掩模通过干蚀刻在基础层上形成沟槽结构。沿着结构的电场分布由沟槽的数量和尺寸控制。电场通过沟槽结构分布,因此电场在基部和台面边缘的拥挤被减小。在沟槽的深度,宽度,间距和数量方面对设计进行了优化,以实现4.5 kV的击穿电压(V_b),这是理论值的85%。使用更精细的光刻分辨率可获得更高的效率,从而导致更小的间距,更大的数量和更窄的沟槽。对于有源面积为0.04 mm2的小面积BJT,测量的比导通电阻(R_(on))为20mΩ.cm〜2。所制造器件的BV-R_(on)非常接近SiC极限,远远超过了最佳SiC MOSFET。

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